Books by "David W Chang"
4 books found
This SpringerBrief sheds new light on bioactive materials from marine extremophiles. It deals with all aspects of the chemical compounds produced by organisms living under extreme conditions that may have potential as drugs or lead to novel drugs for human use.
Boolean Circuit Rewiring
by Tak-Kei Lam, Wai-Chung Tang, Xing Wei, Yi Diao, David Yu-Liang Wu
2016 · John Wiley & Sons
Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called “rewiring” and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today’s semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs. Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field Provides complete coverage of rewiring from an introductory to intermediate level Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples Readers can directly apply the described techniques to real-world VLSI design issues Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and “set of pairs of functions to be distinguished” (SPFD) based rewiring are also discussed A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.
Fully updated to meet the demands of the 21st-century surgeon, Lower Extremity, Trunk and Burns Surgery, Volume 4 of Plastic Surgery, 3rd Edition, provides you with the most current knowledge and techniques across your field, allowing you to offer every patient the best possible outcome. Access all the state-of-the-art know-how you need to overcome any challenge you may face and exceed your patients’ expectations. Consult this title on your favorite e-reader, conduct rapid searches, and adjust font sizes for optimal readability. Compatible with Kindle®, nook®, and other popular devices. Apply the very latest advances in extremity, trunk, and burn plastic surgery and ensure optimal outcomes with evidence-based advice from a diverse collection of world-leading authorities. Purchase this volume individually or own the entire set, with the ability to search across all six volumes online! Apply the latest techniques in lower extremity, trunk, and burn reconstruction, including microsurgical lymphatic reconstruction, super microsurgery, sternal fixation, and more. Know what to look for and what results you can expect with over 950 photographs and illustrations. See how to perform key techniques with 12 surgical videos online. Access the complete, fully searchable contents online, download all the tables and figures, and take advantage of additional content and images at www.expertconsult.com!
Manufacturability Aware Routing in Nanometer VLSI
by David Z. Pan, Minsik Cho, Kun Yuan
2010 · Now Publishers Inc
This paper surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical-mechanical polishing, and antenna-effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) as well as construct-by-correction (i.e., post-routing optimization). This paper will provide a holistic view of key design for manufacturability issues in nanometer VLSI routing.